At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Senior PCIE/CXL Applications Engineering
This position requires a highly motivated and experienced individual to work with Synopsys' customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products utilizing our PCIE & CXL digital IPs. The position offers opportunities to work on Synopsys IIP and the latest industry specifications/applications on various hot market segments like: PCIE GEN-6/7, CXL-3, 112G/224G Serdes.
The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges across all the ASIC design cycle (From PCIE/CXL IPs architecture/integration and up to the silicon bring-up).
We are looking for rising STAR who can do a change, motivated engineer with deep ASIC related knowledge and experience who can help our key world-wide customers to integrate our cutting-edge technology PCIE/CXL IPs.
The position offering opportunity to be part of world-wide diverse team and providing the option to be in the front of cutting-edge knowledge including interacting with world-wide industry experts and leaders.
Some travels may be required. Key Qualifications This position typically requires at least 10-15 years of related ASIC design experience, but we may also consider candidates with less experience but with the right academic background and knowledge. Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, SI/PI etc.) or silicon bring-up/characterization in a system environment. Advanced Lab related experience like ATE and high-speed interface IPs bring-up. Good communication skills and capabilities to interact with different peers from different geographics. Preferred Experience PCIE/CXL expertise, focusing on specifications knowledge and design verification. PCIE related Lab experience, focusing on PCIE silicon debug aspects (e.g : traces/packets analyzing). Technical knowledge with Interface IP such as PCIe, Ethernet Protocols, Specification, Design, Verification, and Implementation. Excellent organization skills, multi-tasking capabilities, strong communication skills and ability to interact with Key customers including industries leaders. Proven track record in meeting tight schedules and handling multiple projects concurrently, including proven leadership skills. Deep high-level understanding and proven experience as technical lead in different ASIC design cycles like: HIP/SIP integration into high scale SOCs, Design verification flows, physical implementation including timing closure, SI/PI, Silicon bring-up in Lab. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
